In a conventional logic circuit there are various kinds of circuit systems including those constituted by bipolar transistors and CMOS transistors.
FIG. 1 is a diagram of a NAND gate circuit constituted by bipolar transistors. With respect to the NAND gate shown in FIG. 1, an input stage having two input terminals A and B which include diode transistor logic having diodes D.sub.1 and D.sub.2 and schottky transistors (referred to as S transistors in the following description) Q.sub.1 and Q.sub.2 of NPN type, and an output stage which has an S transistor Q.sub.3 and a bipolar transistor Q.sub.4 (referred to as a B transistor in the following description) of NPN type which are darlington-connected to each other. The output stage also has an S transistor Q.sub.5 connected to the transistors Q.sub.3 and Q.sub.4. An output terminal OUT is connected to the connecting point between the B transistor Q.sub.4 and the S transistor Q.sub.5.
When the logic gate is configured by the B transistor, a logic gate having drive ability for high load and operated at a high speed can be provided by a large transfer conductance of the B transistor which is one of the characteristics thereof.
In FIG. 1, when both the input terminals A and B are in a high level state of voltage, the S transistor Q.sub.1 is turned on so that an electric path is formed from a voltage source V.sub.cc through a resistor R.sub.1, S transistor Q.sub.1 and a resistor R.sub.2 to ground. Further, the S transistor Q.sub.2 is turned on so that an electric current flows along a path from the voltage source V.sub.cc through a resistor R.sub.3, S transistor Q.sub.2 to the base terminal of S transistor Q.sub.5. When either one of the input terminals A and B is in a low level state of voltage, e.g., the input terminal A is in the low level state, an electric current flows along a path from the voltage source V.sub.cc through a resistor R.sub.4 to a diode D.sub.1.
Accordingly, even when the circuit is in the stationary state, the electric current path mentioned above is formed in the circuit so that the power consumption is increased. When the electric current is reduced to decrease the power consumption, the circuit is not operated at a high speed. Therefore, the circuit has been constructed by CMOS transistors to operate the circuit at a high speed and reduce the power consumption.
FIG. 2 is a diagram of a NAND gate circuit configured by CMOS transistors. In the NAND gate circuit, an input stage having two input terminals C and D is constructed by a P channel MOS transistor P.sub.1 (referred to as PMOS in the following description) and N channel MOS transistors (referred to as NMOS in the following description) N.sub.1 and N.sub.2 connected in series to each other, a PMOS transistor P.sub.2, an NMOS transistor N.sub.3 and an NMOS transistor N.sub.4 which are connected in series to each other and connected in parallel to PMOS transistor P.sub.1, NMOS transistor N.sub.1 and NMOS transistor N.sub.2. An output stage of the NAND gate circuit is constructed by an inverter circuit composed of a PMOS transistor P.sub.3 and an NMOS transistor N.sub.5, an inverter circuit composed of a PMOS transistor P.sub.4 and an NMOS transistor N.sub.6, and further cascade-connected to the former inverter circuit. An input protecting circuit constituted by diodes D.sub.3, D.sub.4 of PN junction and a resistor R.sub.5, and diodes D.sub.5 and D.sub.6 of PN junction and a resistor R.sub.6, is connected to the respective input terminals C and D.
When the logic circuit is constructed by the CMOS transistors as mentioned above, the current drive ability is reduced and it is difficult to operate the circuit at a high speed since the transfer conductance of the MOS transistor is smaller than that of the bipolar transistor. Accordingly, the output stage of the logic circuit is constructed by inverter circuits having the increased sizes of transistors and being cascade-connected to each other.
However, in such a logic circuit constructed as above, an output signal is delayed by a transfer delay time t.sub.pd of the inverter circuits cascade-connected to each other. Further, when the sizes of the transistors at the output stage are increased, the circuit is increased in size, which is disadvantageous in specifically providing a compact circuit by integration.
Further, when the sizes of the transistors at the output stage are increased, the ON resistances of the transistors are reduced. Accordingly, when an output signal is overshot or undershot, the ON resistances of the transistors cannot absorb the overshoot or undershoot of the output signal in a resonant circuit formed by an inductance component of a wiring connected to an output terminal OUT and a capacity component of a load, thereby generating ringing and causing an error in operation in the worst case.
Therefore, the input protecting circuit of the diodes of the PN junction and resistor is connected to the input terminals C and D, and is efficient with respect to surge noise. However, it is difficult to sufficiently restrict the ringing since the voltage drop V.sub.F in the forward direction of the diodes of PN junction is about 0.7 volt.
As mentioned above, when the logic gate is constructed by bipolar transistors, the load-drive ability and the speed of operation are improved, but the power consumption is increased, and the speed of operation is reduced when the power consumption is reduced.
When the logic gate is constructed by only CMOS transistors, the power consumption can be reduced, but the load-drive ability is reduced and it is difficult to operate the circuit at a high speed. When the sizes of the transistors at the output stage are increased to improve the load-drive ability, the structure of the circuit is increased in size and it is difficult to sufficiently restrict the ringing. Therefore, in such constructions, it is difficult to reduce power consumption, improve load-drive ability and speed in operation, and restrict ringing.